[all-commits] [llvm/llvm-project] d94d07: [ARM][Thumb2] Fix ADD/SUB invalid writes to SP

[dnsampaio via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d94d079a6a5b12156e4b818c8ba46eb143f335b9
      https://github.com/llvm/llvm-project/commit/d94d079a6a5b12156e4b818c8ba46eb143f335b9
  Author: Diogo Sampaio <diogo.sampaio at arm.com>
  Date:   2020-01-14 (Tue, 14 Jan 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
    M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
    M llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
    M llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
    A llvm/test/CodeGen/Thumb2/bug-subw.ll
    M llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
    M llvm/test/CodeGen/Thumb2/mve-stacksplot.mir
    M llvm/test/CodeGen/Thumb2/peephole-addsub.mir
    M llvm/test/CodeGen/Thumb2/peephole-cmp.mir
    A llvm/test/CodeGen/Thumb2/t2peephole-t2ADDrr-to-t2ADDri.ll
    M llvm/test/MC/ARM/basic-thumb2-instructions.s
    M llvm/test/MC/ARM/invalid-addsub.s
    M llvm/test/MC/ARM/negative-immediates.s
    M llvm/test/MC/ARM/register-token-source-loc.s
    M llvm/test/MC/ARM/thumb-diagnostics.s
    M llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt
    M llvm/test/MC/Disassembler/ARM/thumb-tests.txt
    M llvm/test/MC/Disassembler/ARM/thumb2-v8.txt
    M llvm/test/MC/Disassembler/ARM/thumb2.txt
    A llvm/test/tools/llvm-mca/ARM/simple-cortex-m33.s

  Log Message:
  -----------
  [ARM][Thumb2] Fix ADD/SUB invalid writes to SP

Summary:
This patch fixes pr23772  [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80".
The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable.
To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP).
Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations.
When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant )
It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt).

Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb

Reviewed By: efriedma

Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70680