[all-commits] [llvm/llvm-project] a43b00: [SelectionDAG] ComputeKnownBits - merge getValidMi...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a43b0065c5c78eba3fb83881fb628f5b8182db64
      https://github.com/llvm/llvm-project/commit/a43b0065c5c78eba3fb83881fb628f5b8182db64
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-01-14 (Tue, 14 Jan 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
    M llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll

  Log Message:
  -----------
  [SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and generic ISD::SRL handling.

As mentioned by @nikic on rGef5debac4302 (although that was just about SHL), we can merge the guaranteed top zero bits from the shifted value, and then, if a min shift amount is known, zero out the top bits as well.

SHL tests / handling will be added in a follow up patch.


  Commit: fd42a4ac7a69adb92f87c7fa927509f177dcc6ca
      https://github.com/llvm/llvm-project/commit/fd42a4ac7a69adb92f87c7fa927509f177dcc6ca
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-01-14 (Tue, 14 Jan 2020)

  Changed paths:
    M llvm/test/CodeGen/X86/combine-shl.ll

  Log Message:
  -----------
  [X86][SSE] Add add(shl(and(x,c1),c2),c3) test case with non-uniform shift value

As mentioned by @nikic on rGef5debac4302, we should merge the guaranteed top zero bits from the shifted value and min shift amount code so they can both set the high bits to zero.


Compare: https://github.com/llvm/llvm-project/compare/e73b20c57dc7...fd42a4ac7a69