[all-commits] [llvm/llvm-project] db7c92: AMDGPU: Add register class to DS_SWIZZLE_B32 pattern
Matt Arsenault via All-commits
all-commits at lists.llvm.org
Thu Jan 9 07:29:39 PST 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: db7c92077963195df0807e976cc916b5c6e29a05
https://github.com/llvm/llvm-project/commit/db7c92077963195df0807e976cc916b5c6e29a05
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
AMDGPU: Add register class to DS_SWIZZLE_B32 pattern
Reduces diff for a future patch.
Commit: 0274ed9dc75a0efb2b6130122226ee45f7e57dde
https://github.com/llvm/llvm-project/commit/0274ed9dc75a0efb2b6130122226ee45f7e57dde
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/test/TableGen/GlobalISelEmitter.td
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
TableGen/GlobalISel: Fix slightly wrong generated comment
Commit: 3952748ffdf017f83faddcb1240cb36cb4bb9c5b
https://github.com/llvm/llvm-project/commit/3952748ffdf017f83faddcb1240cb36cb4bb9c5b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
Log Message:
-----------
AMDGPU/GlobalISel: Fix add of neg inline constant pattern
Commit: d964086c62422771c1d6dbe66ee8ea06e8f834b2
https://github.com/llvm/llvm-project/commit/d964086c62422771c1d6dbe66ee8ea06e8f834b2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Log Message:
-----------
AMDGPU/GlobalISel: Add equiv xform for bitcast_fpimm_to_i32
Only partially fixes one pattern import.
Commit: 79450a4ea26a0e9731eaf2629f6dd8c1ffd8f407
https://github.com/llvm/llvm-project/commit/79450a4ea26a0e9731eaf2629f6dd8c1ffd8f407
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Log Message:
-----------
AMDGPU/GlobalISel: Add selectVOP3Mods_nnan
This doesn't enable any new imports yet, but moves the fmed patterns
from failing on this to hitting the "complex suboperand referenced
more than once" limitation in tablegen.
Commit: e71af775684a83f0d1d05ab5225d36830d5aa87e
https://github.com/llvm/llvm-project/commit/e71af775684a83f0d1d05ab5225d36830d5aa87e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Log Message:
-----------
AMDGPU/GlobalISel: Add IMMPopCount xform
Partially fixes BFE pattern import.
Commit: 7d677421607cbfdd8d1e96275c613d3db8a0e51f
https://github.com/llvm/llvm-project/commit/7d677421607cbfdd8d1e96275c613d3db8a0e51f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
Log Message:
-----------
AMDGPU/GlobalISel: Fix import of zext of s16 op patterns
Commit: c1d4963b447c9330c2ad50bb73bb93f9a42c9641
https://github.com/llvm/llvm-project/commit/c1d4963b447c9330c2ad50bb73bb93f9a42c9641
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
Log Message:
-----------
AMDGPU: Use new PatFrag system for d16 load nodes
Commit: 3766f4baccac5cc17680ad4cefd1d5a0d3ba2870
https://github.com/llvm/llvm-project/commit/3766f4baccac5cc17680ad4cefd1d5a0d3ba2870
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
AMDGPU: Use new PatFrag system for d16 stores
Commit: c66b2e1c87ecde72eb37d3452ec9c1b8766ede30
https://github.com/llvm/llvm-project/commit/c66b2e1c87ecde72eb37d3452ec9c1b8766ede30
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/R600Instructions.td
Log Message:
-----------
AMDGPU: Eliminate more legacy codepred address space PatFrags
These should now be limited to R600 code.
Commit: 9ffd0ed838191247e0da7df5e28e54a5129e76a7
https://github.com/llvm/llvm-project/commit/9ffd0ed838191247e0da7df5e28e54a5129e76a7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-01-09 (Thu, 09 Jan 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
Log Message:
-----------
AMDGPU/GlobalISel: Fix import of integer med3
This isn't too useful now, since nothing is currently trying to form
min/max from cmp+select.
Compare: https://github.com/llvm/llvm-project/compare/9704ba652a00...9ffd0ed83819
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