[all-commits] [llvm/llvm-project] c953e0: [CodeGen] Increase the size of a SmallVector

[jayfoad via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c953e061b410163bc54771f186176a92aac04008
      https://github.com/llvm/llvm-project/commit/c953e061b410163bc54771f186176a92aac04008
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2019-11-15 (Fri, 15 Nov 2019)

  Changed paths:
    M llvm/lib/CodeGen/MachineInstr.cpp

  Log Message:
  -----------
  [CodeGen] Increase the size of a SmallVector

The SmallVector reserve() call in
MachineInstrExpressionTrait::getHashValue accounted for over 3% of all
calls to malloc() when I compiled a bunch of graphics shaders for the
AMDGPU target. Its initial size was only enough for machine instructions
with up to 7 operands, but for AMDGPU 8 and 10 operands are very common.
Here's a histogram of number of operands for each call to getHashValue,
gathered from the same collection of shaders:

1  13503
2  254273
3  135781
4  422508
5  614997
6  194953
7  287248
8  1517255
9  31218
10 1191269
11 70731
12 24
13 77
15 84
17 4692
27 16
33 705
49 6

Typical instructions with 8 and 10 operands are floating point
arithmetic and multiply-accumulate instructions like:

%83:vgpr_32 = V_MUL_F32_e64 0, killed %82:vgpr_32, 0, killed %81:vgpr_32, 0, 0, implicit $exec
%330:vgpr_32 = V_MAC_F32_e64 0, killed %327:vgpr_32, 0, killed %329:sgpr_32, 0, %328:vgpr_32(tied-def 0), 0, 0, implicit $exec

Differential Revision: https://reviews.llvm.org/D70301