[all-commits] [llvm/llvm-project] 1d7f79: [MIPS GlobalISel] MSA vector generic and builtin s...

[petar-avramovic via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 1d7f79c0171df921e5519c7f19a94d9a53c7d248
      https://github.com/llvm/llvm-project/commit/1d7f79c0171df921e5519c7f19a94d9a53c7d248
  Author: Petar Avramovic <Petar.Avramovic at rt-rk.com>
  Date:   2019-10-24 (Thu, 24 Oct 2019)

  Changed paths:
    M llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
    M llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
    A llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div_vec.mir
    A llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec.mir
    A llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec_builtin.mir
    A llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div_vec.ll
    A llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div_vec_builtin.ll
    A llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir

  Log Message:
  -----------
  [MIPS GlobalISel] MSA vector generic and builtin sdiv, srem, udiv, urem

Select vector G_SDIV, G_SREM, G_UDIV and G_UREM for MIPS32 with MSA. We
have to set bank for vector operands to fprb and selectImpl will do the
rest. __builtin_msa_div_s_<format>, __builtin_msa_mod_s_<format>,
__builtin_msa_div_u_<format> and __builtin_msa_mod_u_<format> will be
transformed into G_SDIV, G_SREM, G_UDIV and G_UREM in legalizeIntrinsic
respectively and selected in the same way.

Differential Revision: https://reviews.llvm.org/D69333