[all-commits] [llvm/llvm-project] 952908: [MIParser] Set RegClassOrRegBank during instructio...

[petar-avramovic via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 95290827d7d01c63ac57b2cf5204215ba4ee4b06
      https://github.com/llvm/llvm-project/commit/95290827d7d01c63ac57b2cf5204215ba4ee4b06
  Author: Petar Avramovic <Petar.Avramovic at rt-rk.com>
  Date:   2019-10-22 (Tue, 22 Oct 2019)

  Changed paths:
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir

  Log Message:
  -----------
  [MIParser] Set RegClassOrRegBank during instruction parsing

MachineRegisterInfo::createGenericVirtualRegister sets
RegClassOrRegBank to static_cast<RegisterBank *>(nullptr).
MIParser on the other hand doesn't. When we attempt to constrain
Register Class on such VReg, additional COPY is generated.
This way we avoid COPY instructions showing in test that have MIR
input while they are not present with llvm-ir input that was used
to create given MIR for a -run-pass test.

Differential Revision: https://reviews.llvm.org/D68946

llvm-svn: 375502