[all-commits] [llvm/llvm-project] 7015a5: [InstCombine] conditional sign-extend of high-bit-...

[Roman Lebedev via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 7015a5c54b53d8d2297a3aa38bc32aab167bdcfc
      https://github.com/llvm/llvm-project/commit/7015a5c54b53d8d2297a3aa38bc32aab167bdcfc
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2019-10-20 (Sun, 20 Oct 2019)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
    M llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll

  Log Message:
  -----------
  [InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern.

In this pattern, all the "magic" bits that we'd `add` are all
high sign bits, and in the value we'd be adding to they are all unset,
not unexpectedly, so we can have an `or` there:
https://rise4fun.com/Alive/ups

It is possible that `haveNoCommonBitsSet()` should be taught about this
pattern so that we never have an `add` variant, but the reasoning would
need to be recursive (because of that `select`), so i'm not really sure
that would be worth it just yet.

llvm-svn: 375378