[all-commits] [llvm/llvm-project] 7015a5: [InstCombine] conditional sign-extend of high-bit-...
Roman Lebedev via All-commits
all-commits at lists.llvm.org
Sun Oct 20 13:52:00 PDT 2019
Author: Roman Lebedev <lebedev.ri at gmail.com>
Date: 2019-10-20 (Sun, 20 Oct 2019)
[InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern.
In this pattern, all the "magic" bits that we'd `add` are all
high sign bits, and in the value we'd be adding to they are all unset,
not unexpectedly, so we can have an `or` there:
It is possible that `haveNoCommonBitsSet()` should be taught about this
pattern so that we never have an `add` variant, but the reasoning would
need to be recursive (because of that `select`), so i'm not really sure
that would be worth it just yet.
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