[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend

[James Y Knight via llvm-dev]

Sounds like a good idea to me! It seems there's plenty of interest in this
architecture.

>From a quick glance at your existing code, it looks like you haven't added
any llvm tests -- that'll certainly be a requirement.  But barring some
particular reason why it's not feasible, I think that having object-file
generation working is basically considered a requirement for new
architectures. (It's also not clear to me why you cannot with your current
code, it looks like instruction definitions already have their encodings
specified and such).

If you haven't yet, you ought to check out at the great patch series
that Alex Bradbury created to demonstrate the addition of RISCV support to
LLVM, as a guide to what order it probably makes sense to make the changes,
and how to split the changes into reviewable pieces for upstreaming:
https://github.com/lowRISC/riscv-llvm

I'd suggest as your first step, you should work on getting just the Asm/MC
layer rebased onto trunk and working for the core ISA for your target --
able to parse and print assembly, both textual and object files -- with a
full suite of test-cases at each step. Just like the first ~10 patches in
the above patchset.



On Wed, Mar 6, 2019 at 6:29 AM Andrei Safronov via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Hello,
>
> I'm from Espressif Systems company, software department. Our company
> develops processors based on Xtensa architecture like ESP32 and ESP8266. We
> propose the integration of a backend targeting Xtensa architecture.
>
> We started to develop LLVM Xtensa backend almost a year ago. The reason
> was that we saw a demand from our large developers community. Currently
> only GNU compiler supports Xtensa architecture. The company has approved me
> to develop and maintain Xtensa backend.
>
> We already have the initial version of the Xtensa backend, based on LLVM
> Compiler Infrastructure, release 6.0.0. It was successfully tested using
> GCC torture testsuite and multiple applications.
>
> These are the links to LLVM and Clang repositories.
>
> https://github.com/espressif/llvm-xtensa
> https://github.com/espressif/clang-xtensa
>
> Current version can generate Xtensa assembly code as output, not object
> files yet, and has to be used together with GNU Binutils and GCC-built
> libraries to create object and binary files.
>
> Xtensa backend features implemented:
>
> - Xtensa target description(Xtnesa.td, XtensaTargetMachine.cpp,
> XtensaSubTarget.cpp)
> - ISA desciption (XtensaInstrInfo.td, XtensaInstrFormats.td,
> XtensaREgisterInfo.td)
> - Xtensa Call ABI (XtensaCallingConv.td, XtensaFrameLowering.cpp)
> - ASM printer/parser(XtesaAsmPrinter.cpp, XtensaInstrPrinter.cpp,
> XtensaAsmParser.cpp)
>
> Xtensa architecture features implemented in compiler:
>
> - Xtensa Core Architecture instructions
> - Code Density option
> - Windowed Register option
> - Floating-Point Coprocessor option
> - Boolean option (only a subset of instructions)
> - Thread Pointer option
> - atomic operations
>
> Current Xtensa target list:
>
> - support Xtensa LX6 target (ESP32) by default
>
> Compiler optimization levels include O0/O1/O2/O3/Os options.
>
> With LLVM community approval, my next plans will be
>
> - rebasing on the upstream version of LLVM.
> - object code generation (XtensaMC package)
> - implement test cases
> - support for LX106 target (ESP8266)
> - improvements of generated code performance
> - support for zero-overhead loop option
> - MAC16 option
>
> There were some discussions about implementation of the Xtensa backend and
> attempt to implement it:
> http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html
> http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html
>
> Also there were attempts to implement a LLVM Xtensa backend, but recently
> I found only one actual link:
> https://github.com/jdiez17/llvm-xtensa
>
> All comments and suggesions are welcome!
>
> Andrei Safronov
>
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> llvm-dev at lists.llvm.org
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>
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