<div dir="ltr"><div dir="ltr"><div dir="ltr">Sounds like a good idea to me! It seems there's plenty of interest in this architecture.<div><br></div><div>From a quick glance at your existing code, it looks like you haven't added any llvm tests -- that'll certainly be a requirement. But barring some particular reason why it's not feasible, I think that having object-file generation working is basically considered a requirement for new architectures. (It's also not clear to me why you cannot with your current code, it looks like instruction definitions already have their encodings specified and such).</div><div><br></div><div>If you haven't yet, you ought to check out at the great patch series that Alex Bradbury created to demonstrate the addition of RISCV support to LLVM, as a guide to what order it probably makes sense to make the changes, and how to split the changes into reviewable pieces for upstreaming: <a href="https://github.com/lowRISC/riscv-llvm" target="_blank">https://github.com/lowRISC/riscv-llvm</a></div><div><br></div><div><div>I'd suggest as your first step, you should work on getting just the Asm/MC layer rebased onto trunk and working for the core ISA for your target -- able to parse and print assembly, both textual and object files -- with a full suite of test-cases at each step. Just like the first ~10 patches in the above patchset.</div><br class="gmail-Apple-interchange-newline"></div><div><br></div></div></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Mar 6, 2019 at 6:29 AM Andrei Safronov via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<div bgcolor="#FFFFFF">
<p>
</p>
<div class="gmail-m_-3906164681750564834gmail-m_715095656130124833moz-text-flowed" style="font-family:-moz-fixed;font-size:14px" lang="x-unicode">Hello,
<br>
<br>
I'm from Espressif Systems company, software department. Our
company develops processors based on Xtensa architecture like
ESP32 and ESP8266. We propose the integration of a backend
targeting Xtensa architecture.
<br>
<br>
We started to develop LLVM Xtensa backend almost a year ago. The
reason was that we saw a demand from our large developers
community. Currently only GNU compiler supports Xtensa
architecture. The company has approved me to develop and maintain
Xtensa backend.
<br>
<br>
We already have the initial version of the Xtensa backend, based
on LLVM Compiler Infrastructure, release 6.0.0. It was
successfully tested using GCC torture testsuite and multiple
applications.
<br>
<br>
These are the links to LLVM and Clang repositories.
<br>
<br>
<a class="gmail-m_-3906164681750564834gmail-m_715095656130124833moz-txt-link-freetext" href="https://github.com/espressif/llvm-xtensa" target="_blank">https://github.com/espressif/llvm-xtensa</a>
<br>
<a class="gmail-m_-3906164681750564834gmail-m_715095656130124833moz-txt-link-freetext" href="https://github.com/espressif/clang-xtensa" target="_blank">https://github.com/espressif/clang-xtensa</a>
<br>
<br>
Current version can generate Xtensa assembly code as output, not
object files yet, and has to be used together with GNU Binutils
and GCC-built libraries to create object and binary files.
<br>
<br>
Xtensa backend features implemented:
<br>
<br>
- Xtensa target description(Xtnesa.td, XtensaTargetMachine.cpp,
XtensaSubTarget.cpp)
<br>
- ISA desciption (XtensaInstrInfo.td, XtensaInstrFormats.td,
XtensaREgisterInfo.td)
<br>
- Xtensa Call ABI (XtensaCallingConv.td, XtensaFrameLowering.cpp)
<br>
- ASM printer/parser(XtesaAsmPrinter.cpp, XtensaInstrPrinter.cpp,
XtensaAsmParser.cpp)
<br>
<br>
Xtensa architecture features implemented in compiler:
<br>
<br>
- Xtensa Core Architecture instructions
<br>
- Code Density option
<br>
- Windowed Register option
<br>
- Floating-Point Coprocessor option
<br>
- Boolean option (only a subset of instructions)
<br>
- Thread Pointer option
<br>
- atomic operations
<br>
<br>
Current Xtensa target list:
<br>
<br>
- support Xtensa LX6 target (ESP32) by default
<br>
<br>
Compiler optimization levels include O0/O1/O2/O3/Os options.
<br>
<br>
With LLVM community approval, my next plans will be
<br>
<br>
- rebasing on the upstream version of LLVM.
<br>
- object code generation (XtensaMC package)
<br>
- implement test cases
<br>
- support for LX106 target (ESP8266)
<br>
- improvements of generated code performance
<br>
- support for zero-overhead loop option
<br>
- MAC16 option
<br>
<br>
There were some discussions about implementation of the Xtensa
backend and attempt to implement it:
<br>
<a class="gmail-m_-3906164681750564834gmail-m_715095656130124833moz-txt-link-freetext" href="http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html" target="_blank">http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html</a>
<br>
<a class="gmail-m_-3906164681750564834gmail-m_715095656130124833moz-txt-link-freetext" href="http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html" target="_blank">http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html</a>
<br>
<br>
Also there were attempts to implement a LLVM Xtensa backend, but
recently I found only one actual link:
<br>
<a class="gmail-m_-3906164681750564834gmail-m_715095656130124833moz-txt-link-freetext" href="https://github.com/jdiez17/llvm-xtensa" target="_blank">https://github.com/jdiez17/llvm-xtensa</a>
<br>
<br>
All comments and suggesions are welcome!
<br>
<br>
Andrei Safronov
<br>
<br>
</div>
</div>
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