[llvm-dev] Handling floating point exceptions in RISC-V using compiler

Alex Bradbury via llvm-dev llvm-dev at lists.llvm.org
Sat Jun 29 02:20:52 PDT 2019

On Sat, 29 Jun 2019 at 09:53, faisal via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Hi,
> I am interested in handling floating point exceptions for a RISC-V
> hardware.RISC-V ISA does not mandate generating interrupts when any
> floating point exception occurs. Only corresponding bit in floating
> point control and status register is set when any floating point
> exception occurs.
> So, i want compiler to add checks for floating point exceptions.

Hi Faisal. By default, LLVM will perform transformations with the
assumption that floating point exceptions are ignored (see
https://llvm.org/docs/LangRef.html#floating-point-environment). So
even if you altered the lowering for FP operations to check FPCSR, it
would be non-exhaustive. I recommend looking at the constrained
floating point intrinsics, which by my understanding would be a better
starting point for the sort of lowering you're describing

Are you using the Clang frontend? I don't know if there's been new
updates since <https://lists.llvm.org/pipermail/llvm-dev/2018-May/123529.html>,
but you'll want Clang to support -ftrapping-math which I don't think
it does yet.



More information about the llvm-dev mailing list