[llvm-dev] Handling floating point exceptions in RISC-V using compiler
faisal via llvm-dev
llvm-dev at lists.llvm.org
Sat Jun 29 01:53:13 PDT 2019
I am interested in handling floating point exceptions for a RISC-V
hardware.RISC-V ISA does not mandate generating interrupts when any
floating point exception occurs. Only corresponding bit in floating
point control and status register is set when any floating point
So, i want compiler to add checks for floating point exceptions.
I think this requires changing how a compiler performs some basic
After every operation which may lead to floating point exceptions like
addition and multiplication, status bits in FPCSR register should be
checked and branching should occur if any of the bits is set.
I plan to make these changes in llvm for RISC-V and then do the same for
gcc for RISC-V. This most likely will result in making things slow(
significantly ) as number of assembly instructions will increase.
I guess that changes has to be made in the code responsible for
generating assembly from RTL. It would be very helpful if i can get some
hints on how should i proceed.
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