[llvm-dev] Can register class effect ISel pattern?

Daniel Sanders via llvm-dev llvm-dev at lists.llvm.org
Thu Aug 1 11:51:40 PDT 2019

Hi Nancy,

No, in general register classes haven't been assigned yet when instruction selection is trying to match the SelectionDAG representation. When you specify a register class in a pattern you're actually specifying the types that can be stored in that register class.

GlobalISel is slightly different though. GlobalISel adds a 'register bank' concept which is available to the instruction selector when it tries to match. In this case specifying a register class in a pattern specifies the types that can be stored in the class as well as the bank the class belongs to. There's another pass called Register Bank Allocator that assigns register banks in advance of running instruction selection.

Hope that helps

> On Jul 31, 2019, at 20:31, Nancy via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> Hi,
> Can register class effect Instruction selection prefer in ISel pattern?
> Example:
> Same LLVM IR add instruction, same data type i32, different asm
> instruction, different register class  GPR,  SGPR
> if one operator comes from GPR register class, it selects GPR "add" instruction
> if all operators come from SGPR register class, it select SGPR "add" instruction
> -- 
> Best Regards,
> Yu Rong Tan
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