[llvm-dev] add new instruction format
ComputerFreak via llvm-dev
llvm-dev at lists.llvm.org
Wed Jun 20 18:06:55 PDT 2018
Im trying to add RISC V Store Instruction for an Experiment on my Target.
The thing is, llvm Store Format gets Register and Pointer Type Operand.
beside this, RISC-V Store Instruction takes source Register, Base Register and offset immediate type. So this takes 3 leafs.
In this case, should I make new SelectionDAG Node in this case? or use BuildMI Instruction to add new Register?
P.S. if using BuildMI function to modify Instruction, is there a way to use random Register?
because when looking some BuildMI function usage, they seem using the specific Register
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the llvm-dev