[llvm-dev] Disabling DAGCombine's specific optimization

[Matt Arsenault via llvm-dev]

> On May 15, 2017, at 07:54, vivek pandya via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> Hello LLVM Developers,
> 
> I am working on an architecture which have one bit shift operation if barrel shiftier hardware is not present in such cases some DAGCombine optimizations reduces performance of certain benchmarks upto 5% for example consider follwing optimization:
> fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
> Here it introduce 2 shift operations and when barrel shiftier is not present these shifts will be converted to loops thus making it worst. I am sure there few architectures which have similar features. So how to disable these kind of optimizations in DAGCombine particularly when I want build and use LLVM for more than one target ?
> 
> Sincerely,
> Vivek
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Sounds to me like this combine is missing a TLI.isOperationLegal(ISD::LSHR) or similar check

-Matt
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