<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On May 15, 2017, at 07:54, vivek pandya via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Hello LLVM Developers,<div class=""><br class=""></div><div class="">I am working on an architecture which have one bit shift operation if barrel shiftier hardware is not present in such cases some DAGCombine optimizations reduces performance of certain benchmarks upto 5% for example consider follwing optimization:</div><div class=""><div style="font-family: consolas, 'courier new', monospace; font-size: 14px; line-height: 19px; white-space: pre;" class=""><span style="color:rgb(0,142,0)" class="">fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)</span></div></div><div class="">Here it introduce 2 shift operations and when barrel shiftier is not present these shifts will be converted to loops thus making it worst. I am sure there few architectures which have similar features. So how to disable these kind of optimizations in DAGCombine particularly when I want build and use LLVM for more than one target ?</div><div class=""><br class=""></div><div class="">Sincerely,</div><div class="">Vivek</div></div>
_______________________________________________<br class="">LLVM Developers mailing list<br class=""><a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a><br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev<br class=""></div></blockquote></div><br class=""><div class="">Sounds to me like this combine is missing a TLI.isOperationLegal(ISD::LSHR) or similar check</div><div class=""><br class=""></div><div class="">-Matt</div></body></html>