[llvm-dev] Possible missing DAGCombine opportunity?

陳韋任 via llvm-dev llvm-dev at lists.llvm.org
Mon Jun 19 03:32:22 PDT 2017

Hi All,

  The initial SelectionDAG I have has the following snippet.

    t10: i64,ch = load<LD8[%1](align=4)> t0, t4, undef:i32
            t13: i64 = srl t10, Constant:i32<8>
          t14: i32 = truncate t13

and after DAGCombine the SelectionDAG becomes,

    t10: i64,ch = load<LD8[%1](align=4)> t0, t4, undef:i32
            t30: i32 = truncate t10
          t36: i32 = srl t30, Constant:i32<6>

Here I want to load i32 if possible. Can above pattern be combined further?
If not, I find it's because srl and truncate be swapped, and the truncate in
the middle blocks DAGCombine combine srl and load. Any idea on why
DAGCombine perform this way?



Wei-Ren Chen (陳韋任)
Homepage: https://people.cs.nctu.edu.tw/~chenwj
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