[llvm-dev] Some questions about software pipeline in LLVM 4.0.0
Brendon Cahoon via llvm-dev
llvm-dev at lists.llvm.org
Tue Jun 27 07:26:05 PDT 2017
> If we see these kind of copies frequently enough, do you think it is
worthwhile to work on the algorithm, so these instructions are predicted and
taken into account during the scheduling?
if you do see them frequently, then it would be worthwhile to find a way to
eliminate them. I'm not sure how easy it would be to predict them though
when the MII is computed. My guess is that you want some solution where the
generated schedule doesn't require the extra copies. Without some more
information, it's hard to see why the algorithm is generating a schedule
that requires extra copies so frequently.
> Or maybe we already do this and I am not aware of it?
In some cases, the pipeliner does attempt to eliminate unnecessary copies.
For Hexagon, or any machine that allows multiple instructions per cycle, the
pipeliner attempts to order the generated instructions to minimize copies.
For example, Hexagon allows up to 4 instructions to execute "in parallel".
So, in the same cycle, there can be a use of a register and a definition of
that same register (the uses are read first, then the definition occurs). In
effect, the use is for the value generated in the previous iteration. Since
the pipeliner generates a linear list of instructions (i.e., serial
semantics), the final order needs to make sure that the use is generated
before the definition. Otherwise, an extra copy is generated.
> IIUC, these kind of copies will be generated even if we implement SMS
after register coalescing. Is this correct?
That is correct.
> you don't see it frequently though. Is that correct?
Correct. For Hexagon, we don't see the extra copies very frequently. In
your earlier example though, it would be interesting to see why the
algorithm puts the definition prior to the last use. If possible, its
better to schedule the definition after the last use. Of course, in some
cases, that may/may not generate an efficient schedule.
From: Ehsan Amiri [mailto:ehsan.amiri at huawei.com]
Sent: Tuesday, June 27, 2017 7:57 AM
To: Brendon Cahoon <bcahoon at codeaurora.org>
Cc: llvm-dev at lists.llvm.org
Subject: RE: [llvm-dev] Some questions about software pipeline in LLVM 4.0.0
Thanks for the answer. I completely agree with your comments. The main
reason that I brought up this issue is the following: Inserting a COPY
instruction that cannot be eliminated, means that the loop has an
instruction that was not taken into account during modulo scheduling
analysis. If we see these kind of copies frequently enough, do you think it
is worthwhile to work on the algorithm, so these instructions are predicted
and taken into account during the scheduling? Or maybe we already do this
and I am not aware of it?
Some other remarks/questions:
IIUC, these kind of copies will be generated even if we implement SMS after
register coalescing. Is this correct?
For us, so far we have enabled machine pipeliner for our backend and we see
these kind of copy generated frequently for our workloads. Some times
multiple copies inserted in a relatively small loop. IIUC, you don't see it
frequently though. Is that correct?
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