[llvm-dev] Wide load/store optimization question

陳韋任 via llvm-dev llvm-dev at lists.llvm.org
Fri Jun 16 12:03:05 PDT 2017

> One thing you can do is define a register class that is made up of register
> tuples e.g. r0r1, r2r3, etc., and use that register class for the 64-bit
> load/store instructions.  This will allow you to do the load/store
> merging before register allocation without the register constraints.

​Our backend only support load/store for i64 type, hence i64 is not legal
for us.
I guess Peter's Epiphany arch has similar situation.​

IIRC, LLVM expand load i64 to two load i32. Right now, we have to custom
lowering load i64 to load v2i32, then map v2i32 to the tuple register
to Sparc backend). How can we use the tuple register for those two i32?
​Any existing example?


Wei-Ren Chen (陳韋任)
Homepage: https://people.cs.nctu.edu.tw/~chenwj
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