<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">One thing you can do is define a register class that is made up of register<br>
tuples e.g. r0r1, r2r3, etc., and use that register class for the 64-bit<br>
load/store instructions.  This will allow you to do the load/store<br>
merging before register allocation without the register constraints.</blockquote><div><br></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">​Our backend only support load/store for i64 type, hence i64 is not legal for us.</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">I guess Peter's <span style="font-size:14px;font-family:arial,sans-serif">Epiphany arch</span> has similar situation.​</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif"><br></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">IIRC, LLVM expand load i64 to two load i32. Right now, we have to custom</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">lowering load i64 to load v2i32, then map v2i32 to the tuple register (similar</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">to Sparc backend). How can we use the tuple register for those two i32? </div></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">​Any existing example?</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif"><br></div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">Regards,</div><div class="gmail_default" style="font-family:arial,helvetica,sans-serif">chenwj​</div><div><br></div>-- <br><div class="gmail_signature"><div dir="ltr"><div>Wei-Ren Chen (陳韋任)<br>Homepage: <a href="https://people.cs.nctu.edu.tw/~chenwj" target="_blank">https://people.cs.nctu.edu.tw/~chenwj</a></div></div></div>
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