[llvm-dev] Backend implementation for an architecture with only majority operation instruction

[Matthias Braun via llvm-dev]

I guess this is relevant here: https://en.wikipedia.org/wiki/One_instruction_set_computer

> On Jun 4, 2017, at 7:22 PM, Sean Silva via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> I'm having a hard time grasping what this ISA actually looks like.
> 
> When you say that it has a single instruction that is a majority function, I assume something like this:
> 
> MAJ rDst <- rSrc0, rSrc1, rSrc2
> Semantics:
> for (int i = 0; i < REGISTER_WIDTH; i++) {
>   rDst[i] = maj(rSrc0[i], rSrc1[i], rSrc2[i]);
> }
> Where maj(a, b, c) = (a & b) | (a & c) | (b & c)
> 
> But that doesn't make sense given your question.
> 
> MAJ is a bitwise operation, so how do you implement arithmetic instructions with it? You would need at least one other instruction (such as a bit shift) to establish dependency chains between bits.
> 
> Also, how do you decompose load/store into majority functions? It's not even clear to me what that would actually mean. You need to access the memory/IO bus somehow, and if your only instruction only reads/writes to registers, the only way to do that would be to have special registers that interface to the IO bus?
> 
> -- Sean Silva
> 
> On Thu, Jun 1, 2017 at 8:13 PM, Sreejita saha via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
> Hello everyone,
> 
>  
> 
> I was trying to create an LLVM backend for a processor with a very simple architecture and that does all instructions like load, store, arithmetic and logical instructions using a bunch of majority functions. The processor has only one instruction(majority function) in its ISA and breaks down all other instructions into a number of majority instructions depending on what instruction it is. All the instructions have different combinations of majority operations. Is there any way to implement this without creating a new Selection DAG node for the majority operation?
> 
> I was thinking of creation of a new Selection DAG node and mapping all the other instructions like loads, stores as pseudo instructions and breaking them up. Can someone please help me with this?
> 
>  
> 
> Thanks!
> 
> Sreejita
> 
>  
> 
>  
> 
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> 
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