<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><div class="">I guess this is relevant here: <a href="https://en.wikipedia.org/wiki/One_instruction_set_computer" class="">https://en.wikipedia.org/wiki/One_instruction_set_computer</a></div><br class=""><div><blockquote type="cite" class=""><div class="">On Jun 4, 2017, at 7:22 PM, Sean Silva via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">I'm having a hard time grasping what this ISA actually looks like.<div class=""><br class=""></div><div class="">When you say that it has a single instruction that is a majority function, I assume something like this:</div><div class=""><br class=""></div><div class="">MAJ rDst <- rSrc0, rSrc1, rSrc2</div><div class="">Semantics:</div><div class="">for (int i = 0; i < REGISTER_WIDTH; i++) {</div><div class=""> rDst[i] = maj(rSrc0[i], rSrc1[i], rSrc2[i]);</div><div class="">}</div><div class="">Where maj(a, b, c) = (a & b) | (a & c) | (b & c)<br class=""><div class=""><br class=""></div><div class="">But that doesn't make sense given your question.</div><div class=""><br class=""></div><div class="">MAJ is a bitwise operation, so how do you implement arithmetic instructions with it? You would need at least one other instruction (such as a bit shift) to establish dependency chains between bits.</div><div class=""><br class=""></div><div class="">Also, how do you decompose load/store into majority functions? It's not even clear to me what that would actually mean. You need to access the memory/IO bus somehow, and if your only instruction only reads/writes to registers, the only way to do that would be to have special registers that interface to the IO bus?</div><div class=""><br class=""></div><div class="">-- Sean Silva</div></div></div><div class="gmail_extra"><br class=""><div class="gmail_quote">On Thu, Jun 1, 2017 at 8:13 PM, Sreejita saha via llvm-dev <span dir="ltr" class=""><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank" class="">llvm-dev@lists.llvm.org</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div lang="EN-US" link="blue" vlink="#954F72" class=""><div class="m_8637115130387562025WordSection1"><p class="MsoNormal">Hello everyone,</p><p class="MsoNormal"><u class=""></u> <u class=""></u></p><p class="MsoNormal">I was trying to create an LLVM backend for a processor with a very simple architecture and that does all instructions like load, store, arithmetic and logical instructions using a bunch of majority functions. The processor has only one instruction(majority function) in its ISA and breaks down all other instructions into a number of majority instructions depending on what instruction it is. All the instructions have different combinations of majority operations. Is there any way to implement this without creating a new Selection DAG node for the majority operation?</p><p class="MsoNormal">I was thinking of creation of a new Selection DAG node and mapping all the other instructions like loads, stores as pseudo instructions and breaking them up. Can someone please help me with this?</p><p class="MsoNormal"><u class=""></u> <u class=""></u></p><p class="MsoNormal">Thanks!</p><p class="MsoNormal">Sreejita</p><p class="MsoNormal"><u class=""></u> <u class=""></u></p><p class="MsoNormal"><u class=""></u> <u class=""></u></p><p class="MsoNormal">Sent from <a href="https://go.microsoft.com/fwlink/?LinkId=550986" target="_blank" class="">Mail</a> for Windows 10</p><p class="MsoNormal"><u class=""></u> <u class=""></u></p></div></div><br class="">______________________________<wbr class="">_________________<br class="">
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