[llvm-dev] Backend implementation of an architecture having only majority instructions

Hal Finkel via llvm-dev llvm-dev at lists.llvm.org
Sat Jun 3 23:25:09 PDT 2017


On 06/03/2017 11:18 PM, Sreejita saha wrote:
> Hey Hal,
> The architecture just supports one instruction which could be actually 
> written down as ORs and ANDs and but there is no particular DAG node 
> that it can directly map onto. Is there a way to describe that 
> instruction ? Like if the instruction does the AB+BC+CA(if A, B,C are 
> operands) can this be written somehow in tablegen pattern?

I don't see why not. You can write a TableGen definition for the 
instruction, which does not need to correspond directly to some SDAG 
node (many instructions don't) and then you can map SDAG nodes onto 
combinations of your instruction using other patterns. For example, 
something like this:

def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
            (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
                  (CRAND (CRORC  $rhs, $lhs), $fval))>;

you'll find lots of examples in lib/Target/PowerPC/PPCInstrInfo.td and 
other backends.

  -Hal

>
> Thanks!
> -Sreejita
>
> On Sat, Jun 3, 2017 at 9:02 AM, Hal Finkel via llvm-dev 
> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>
>
>
>     On 06/03/2017 09:32 AM, Sreejita saha via llvm-dev wrote:
>>
>>     Hello everyone,
>>
>>     I was trying to create an LLVM backend for a processor with a
>>     very simple architecture and that does all instructions like
>>     load, store, arithmetic and logical instructions using a bunch of
>>     majority functions. The processor has only one
>>     instruction(majority function) in its ISA and breaks down all
>>     other instructions into a number of majority instructions
>>     depending on what instruction it is. All the instructions have
>>     different combinations of majority operations. Is there any way
>>     to implement this without creating a new Selection DAG node for
>>     the majority operation? Also can i create a selection DAG node in
>>     the backend instruction info itself? If so then how?
>>
>>     I was thinking of creation of a new Selection DAG node and
>>     mapping all the other instructions like loads, stores as pseudo
>>     instructions and breaking them up. Can someone please help me
>>     with this?
>>
>
>     Why don't you just write TableGen patterns to match the various
>     selection-DAG nodes onto the correct combinations of your instruction?
>
>      -Hal
>
>>     Thanks!
>>
>>     Sreejita
>>
>>
>>
>>     _______________________________________________
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>
>     -- 
>     Hal Finkel
>     Lead, Compiler Technology and Programming Languages
>     Leadership Computing Facility
>     Argonne National Laboratory
>
>     _______________________________________________ LLVM Developers
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>
-- 
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory
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