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<div class="moz-cite-prefix">On 06/03/2017 11:18 PM, Sreejita saha
wrote:<br>
</div>
<blockquote
cite="mid:CAMRe-mtCbs64gH2czgy-oAbHKm9CrJw50H7RSOB3rzwyv7G_hA@mail.gmail.com"
type="cite">
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<div dir="ltr">Hey Hal,
<div>The architecture just supports one instruction which could
be actually written down as ORs and ANDs and but there is no
particular DAG node that it can directly map onto. Is there a
way to describe that instruction ? Like if the instruction
does the AB+BC+CA(if A, B,C are operands) can this be written
somehow in tablegen pattern?</div>
</div>
</blockquote>
<br>
I don't see why not. You can write a TableGen definition for the
instruction, which does not need to correspond directly to some SDAG
node (many instructions don't) and then you can map SDAG nodes onto
combinations of your instruction using other patterns. For example,
something like this:<br>
<br>
def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval,
SETLT)),<br>
(CROR (CRAND (CRANDC $lhs, $rhs), $tval),<br>
(CRAND (CRORC $rhs, $lhs), $fval))>;<br>
<br>
you'll find lots of examples in lib/Target/PowerPC/PPCInstrInfo.td
and other backends.<br>
<br>
-Hal<br>
<br>
<blockquote
cite="mid:CAMRe-mtCbs64gH2czgy-oAbHKm9CrJw50H7RSOB3rzwyv7G_hA@mail.gmail.com"
type="cite">
<div dir="ltr">
<div><br>
</div>
<div>Thanks!</div>
<div>-Sreejita</div>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Sat, Jun 3, 2017 at 9:02 AM, Hal
Finkel via llvm-dev <span dir="ltr"><<a
moz-do-not-send="true"
href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p><br>
</p>
<br>
<div class="m_947476482614607550moz-cite-prefix">On
06/03/2017 09:32 AM, Sreejita saha via llvm-dev wrote:<br>
</div>
<blockquote type="cite">
<div dir="auto">
<p style="font-family:sans-serif;font-size:13.696px"><span
style="font-size:13.696px">Hello everyone,</span><br>
</p>
<p style="font-family:sans-serif;font-size:13.696px"> </p>
<p style="font-family:sans-serif;font-size:13.696px">I
was trying to create an LLVM backend for a
processor with a very simple architecture and that
does all instructions like load, store, arithmetic
and logical instructions using a bunch of majority
functions. The processor has only one
instruction(majority function) in its ISA and
breaks down all other instructions into a number
of majority instructions depending on what
instruction it is. All the instructions have
different combinations of majority operations. Is
there any way to implement this without creating a
new Selection DAG node for the majority operation?
Also can i create a selection DAG node in the
backend instruction info itself? If so then how?</p>
<p style="font-family:sans-serif;font-size:13.696px">I
was thinking of creation of a new Selection DAG
node and mapping all the other instructions like
loads, stores as pseudo instructions and breaking
them up. Can someone please help me with this?</p>
</div>
</blockquote>
<br>
</span> Why don't you just write TableGen patterns to
match the various selection-DAG nodes onto the correct
combinations of your instruction?<br>
<br>
-Hal<br>
<br>
<blockquote type="cite">
<div dir="auto">
<p style="font-family:sans-serif;font-size:13.696px"> </p>
<p style="font-family:sans-serif;font-size:13.696px">Thanks!</p>
<p style="font-family:sans-serif;font-size:13.696px">Sreejita</p>
</div>
<br>
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<pre class="m_947476482614607550moz-signature" cols="72">--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory</pre>
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<pre class="moz-signature" cols="72">--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory</pre></body></html>