[llvm-dev] Pre/post-increment addressing mode in LSR
Jamie Hanlon via llvm-dev
llvm-dev at lists.llvm.org
Mon Jan 23 07:14:15 PST 2017
Thanks for the clarification Hal, that’s really useful. We will be sure to upstream any generic work we do on this.
From: Hal Finkel <hfinkel at anl.gov>
Organization: Argonne National Laboratory
Date: Monday, 23 January 2017 at 14:09
To: Jamie Hanlon <Jamie.Hanlon at graphcore.ai>, "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org>
Cc: Jon Chesterfield <jonc at graphcore.ai>
Subject: Re: [llvm-dev] Pre/post-increment addressing mode in LSR
On 01/23/2017 05:52 AM, Jamie Hanlon via llvm-dev wrote:
From what I can gather, there is currently no way for loop strength reduction to target pre- and post-increment addressing modes. This is because the target hook `isLegalAddressingMode` in TargetTransformInfo.h doesn’t allow for pre- and post-increment. There is in fact a comment to that effect on the function prototype: “TODO: handle pre/postinc as well” (see http://llvm.org/docs/doxygen/html/TargetTransformInfo_8h_source.html line 310).
So I was wondering: is there a way to work around this limitation? And are there any plans to add support for pre- and post-increment addressing modes?
It is, unfortunately, a long-standing deficiency. There are some work-arounds in some targets (e.g. lib/Target/PowerPC/PPCLoopPreIncPrep.cpp), but work on this would be appreciated.
Thanks in advance for any help on this.
Jamie Hanlon (from Graphcore, www.graphcore.ai<http://www.graphcore.ai>)
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Lead, Compiler Technology and Programming Languages
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Argonne National Laboratory
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