[llvm-dev] Pre/post-increment addressing mode in LSR
Hal Finkel via llvm-dev
llvm-dev at lists.llvm.org
Mon Jan 23 06:09:45 PST 2017
On 01/23/2017 05:52 AM, Jamie Hanlon via llvm-dev wrote:
> Dear all,
> From what I can gather, there is currently no way for loop strength
> reduction to target pre- and post-increment addressing modes. This is
> because the target hook `isLegalAddressingMode` in
> TargetTransformInfo.h doesn’t allow for pre- and post-increment. There
> is in fact a comment to that effect on the function prototype: “TODO:
> handle pre/postinc as well” (see
> line 310).
> So I was wondering: is there a way to work around this limitation? And
> are there any plans to add support for pre- and post-increment
> addressing modes?
It is, unfortunately, a long-standing deficiency. There are some
work-arounds in some targets (e.g.
lib/Target/PowerPC/PPCLoopPreIncPrep.cpp), but work on this would be
> Thanks in advance for any help on this.
> Jamie Hanlon (from Graphcore, www.graphcore.ai)
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory
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