[llvm-dev] vectorization and vliw(very long instruction word)

via llvm-dev llvm-dev at lists.llvm.org
Mon Feb 20 05:30:59 PST 2017

Thanks, I will modify some transform pass, because my specific target processor. I don't think this a good way, but I think this a easier way. Could I do that?

在2017-02-20 20:47:36,Martin J. O'Riordanmartin.oriordan at movidius.com写道:

Our approach is to let instruction selection and vectorisation happen as if the instruction set was single-issue, and use the post-RA scheduler to fill the VLIW slots with instructions from each of the functional-units [FUs] on a first-come, first-served basis.  This works quite well in conjunction with some mutation patterns that allow an instruction from an alternative FU to be substituted if the preferred FU is busy.


The VLWI nature of the target and the instruction selection and vectorisation are largely orthogonal.  There are scheduling, register allocation and instruction selection decisions that an expert human programmer might do differently, but overall the compiler still produces solutions that are competitive with the solutions determined by expert assembly programmers.




From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of via llvm-dev
Sent: 20 February 2017 02:37
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Subject: [llvm-dev] vectorization and vliw(very long instruction word)


Hello, I want to implement vectorization and vliw(very long instruction word) in my specific dsp ,do you have any advices to me ? 
Thank you very much!
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