[llvm-dev] Patches for parametrized (variable) register classes are up for review
Krzysztof Parzyszek via llvm-dev
llvm-dev at lists.llvm.org
Tue Apr 11 14:40:33 PDT 2017
This is a continuation of the discussion started here:
The motivation was discussed in that thread, and I'll use Hexagon HVX
here as a working example. HVX has two modes, where vector registers are
64- and 128-byte in size. The instruction set is identical in both
cases, that includes the instruction and register encodings. As a matter
of fact, it's possible to have a single binary that works in both modes.
The problem was that due to different register sizes, value types, etc.,
we had to create separate register classes for vector registers in the
64-byte mode and for the 128-byte mode. This forced us to implement two
separate instruction sets that do the exact same thing.
I have posted a series of patches that allow parametrized register
classes, where the register sizes, spill sizes, and value types can be
predicated on a set of subtarget features. The parametrized value types
can also be used in selection patterns.
With these patches we were able to completely remove the extra set of
vector instructions from the Hexagon backend, and use a single set for
Preliminary reorganization of TargetRegisterClass members:
Hexagon changes (showing how the above code can be used):
I have added some selection of people as reviewers, but please feel free
to join in and comment.
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