[llvm-dev] Is it possible to avoid inserting spill/split code in certain instruction sequence in RA?

Dongrui She via llvm-dev llvm-dev at lists.llvm.org
Thu May 12 11:58:32 PDT 2016


Thanks for the suggestion.

For my target making pseudo instructions for this is a bit too much,
because there are many possible combinations. I tried making a bundle in
this situation, and it seems to work fine (with a little bit hacking).


On Mon, May 9, 2016 at 8:35 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> On 5/9/2016 1:30 PM, Dongrui She via llvm-dev wrote:
>> I am working on an out-of-tree target. I am wondering if it is possible
>> to force the register allocator (and/or spiller) to not break certain
>> instruction sequence.
>> For example:
>> phys_reg = MI1 vreg1
>> vreg 2 = MI2 phys_reg
>> Is there a way to tell RA/spiller not to insert COPY or spill between
>> MI1 and MI2?
> You can make a pseudo-instruction that corresponds to the combination
> MI1/MI2, then expand it into the actual instructions in
> TII::expandPostRAPseudo.
> -Krzysztof
> --
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