[llvm-dev] Backend for Non Load/Store Architecture

[Hakan Uyumaz via llvm-dev]

Hi,

I'm trying to write a LLVM backend for a custom CPU architecture. The
architecture that I'm currently working on has no LOAD, STORE instructions
or any register in it, it is working directly on memory. Simple use of an
instruction as follows:

ADD A B

When you use an add operation with two operands which are A and B as above,
it simply sums data on both memory block A and B then writes it into memory
block B. So, you can do any operation without need of any register.

I need to discard LOAD and STORE operations from DAG. Becaues of every
operation need to use memory block adresses as their operands, I cannot
simply discard LOAD and STORE by legalize the SelectionDAG. Is there any
way to define backend for an architecture without LOAD and STORE operations
in LLVM?

Also, immediate operations have non-standard value (14-bit integer) as its
immediate operand. Is there any simple way to use non-standard values?

Thanks in advance.
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