[llvm-dev] Understanding failed assert in reg pressure reduction list scheduler

Elliot Colp via llvm-dev llvm-dev at lists.llvm.org
Fri Jul 29 12:38:31 PDT 2016

Hi all,

I'm currently investigating a bug which is causing an assert to fail in
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp. See
https://llvm.org/bugs/show_bug.cgi?id=28753 for repro information.

To my knowledge, this problem only occurs with the SystemZ target. I'm
trying to determine whether the issue is the result of an edge case in the
scheduling code itself, or if it's a SystemZ target problem. However, I'm
unfamiliar with the scheduling code, so I'm not entirely certain what the
correct behaviour is.

My rough understanding of the problem is that, while attempting to pick a
node to schedule, we're running out of candidates (in
ScheduleDAGRRList::PickNodeToScheduleBottomUp). This causes us to try to
copy a node, and in the process, we call getPhysicalRegisterVT. This
function asserts that the MCInstrDesc associated with the node will have
ImplicitDefs, but in our case, it does not.

In short: does this seem to be a problem of missing information in the
MCInstrDesc, or should we not have arrived at that assert in the first


- Elliot
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