[llvm-dev] Failure to match a DAG after a minor pattern change in a custom Target

Krzysztof Parzyszek via llvm-dev llvm-dev at lists.llvm.org
Fri Feb 19 06:10:09 PST 2016

On 2/18/2016 6:01 PM, Rail Shafigulin via llvm-dev wrote:
>             [(set SR:$rD, (Esenciasetflag (i32 GPR:$rA), (i32
> immSExt16:$imm), (i32 Cond)))]> {

I suspect that the "set SR:$rD" is the problem here.  The Esenciasetflag 
does not have any values that can be assigned to a
register, so it's probably this part that causes the pattern to fail.

Tablegen creates a xxxGenDAGISel.inc file in your target's build 
directory. The "index" numbers that the debugging info shows correspond 
to the numbers in that file.  Here's an example from HexagonGenDAGISel.inc:

/*28*/              OPC_Scope, 88|128,3/*472*/, /*->503*/ // 3 children 
in Scope
/*31*/                OPC_MoveChild, 1,
/*33*/                OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
/*36*/                OPC_RecordChild0, // #2 = $base
/*37*/                OPC_RecordChild1, // #3 = $offset
/*38*/                OPC_MoveChild, 1,
/*40*/                OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
/*43*/                OPC_Scope, 65, /*->110*/ // 7 children in Scope
/*45*/                  OPC_CheckPredicate, 0, // Predicate_u32ImmPred
/*47*/                  OPC_MoveParent,
/*48*/                  OPC_CheckType, MVT::i32,

When the matcher says "false predicate at index 123", you can look at 
the line marked with /*123*/ and see exactly what predicate it was 
checking.  This helps immensely with solving such problems.


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