[llvm-dev] Failure to match a DAG after a minor pattern change in a custom Target
Rail Shafigulin via llvm-dev
llvm-dev at lists.llvm.org
Thu Feb 18 16:01:32 PST 2016
In an attempt to add vector registers to my target, I ran into a problem.
LLVM started to complain about not being able to infer types from the
provided DAG patterns for several classes of instructions. After a
discussion on the llvm-dev mailing list and IRC channel the recommendation
was to make DAG patterns for these classes of instructions more specific.
Which is what was done. However after the changes were made, LLVM stopped
recognizing a particular pattern, saying that it can not match it. Given
that my understanding of DAG patterns is quite weak, I'd appreciate any
help on this. For that matter, any opportunity to learn about LLVM is
welcomed. Original code, modified code as well as the error are provided
below. I can provide more if needed. There were two changes made. One in
the definition of SDT_EsenciaSetFlag and another in SF_RI class
(specifically in its DAG pattern).
Any help is appreciated.
========================= Orignal Code =====================================
def SDT_EsenciaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
def Esencia_CC_LT : PatLeaf<(imm),
[{return (N->getZExtValue() == ISD::SETLT);}]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Esenciasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-0} = imm;
let format = AFrm;
let op2 = op2Val;
}
defm SFLTS : SF<0xc, "l.sflts", Esencia_CC_LT>;
========================= Modified Code
=====================================
def SDT_EsenciaSetFlag : SDTypeProfile<1, 3, [SDTCisSameAs<1, 2>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
def Esencia_CC_LT : PatLeaf<(imm),
[{return (N->getZExtValue() == ISD::SETLT);}]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(set SR:$rD, (Esenciasetflag (i32 GPR:$rA), (i32
immSExt16:$imm), (i32 Cond)))]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-0} = imm;
let format = AFrm;
let op2 = op2Val;
}
multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
def _rr : SF_RR<op2Val, asmstr, Cond>;
def _ri : SF_RI<op2Val, asmstr, Cond>;
}
defm SFLTS : SF<0xc, "l.sflts", Esencia_CC_LT>;
========================= Orignal Match Result
=====================================
Selecting: 0x2ebfa78: glue = EsenciaISD::SET_FLAG 0x2ebee18, 0x2ebef20,
0x2ebf658 [ORD=3] [ID=11]
ISEL: Starting pattern match on root node: 0x2ebfa78: glue =
EsenciaISD::SET_FLAG 0x2ebee18, 0x2ebef20, 0x2ebf658 [ORD=3] [ID=11]
Initial Opcode index to 258
Skipped scope entry (due to false predicate) at index 278, continuing at
292
Skipped scope entry (due to false predicate) at index 293, continuing at
307
Skipped scope entry (due to false predicate) at index 308, continuing at
322
Skipped scope entry (due to false predicate) at index 323, continuing at
337
Skipped scope entry (due to false predicate) at index 338, continuing at
352
Skipped scope entry (due to false predicate) at index 353, continuing at
367
Skipped scope entry (due to false predicate) at index 368, continuing at
382
Skipped scope entry (due to false predicate) at index 383, continuing at
397
Morphed node: 0x2ebfa78: i32,glue = SFLTS_ri 0x2ebee18, 0x2ebf130 [ORD=3]
ISEL: Match complete!
=> 0x2ebfa78: i32,glue = SFLTS_ri 0x2ebee18, 0x2ebf130 [ORD=3]
========================= Failed Match Result
=====================================
Selecting: 0x242d278: glue = EsenciaISD::SET_FLAG 0x242c618, 0x242c720,
0x242ce58 [ORD=3] [ID=11]
ISEL: Starting pattern match on root node: 0x242d278: glue =
EsenciaISD::SET_FLAG 0x242c618, 0x242c720, 0x242ce58 [ORD=3] [ID=11]
Initial Opcode index to 258
Skipped scope entry (due to false predicate) at index 285, continuing at
301
Skipped scope entry (due to false predicate) at index 302, continuing at
318
Skipped scope entry (due to false predicate) at index 319, continuing at
335
Skipped scope entry (due to false predicate) at index 336, continuing at
352
Skipped scope entry (due to false predicate) at index 353, continuing at
369
Skipped scope entry (due to false predicate) at index 370, continuing at
386
Skipped scope entry (due to false predicate) at index 387, continuing at
403
Skipped scope entry (due to false predicate) at index 404, continuing at
420
Match failed at index 424
Continuing at 437
Match failed at index 438
Continuing at 454
Continuing at 455
Skipped scope entry (due to false predicate) at index 466, continuing at
480
Skipped scope entry (due to false predicate) at index 481, continuing at
495
Skipped scope entry (due to false predicate) at index 496, continuing at
510
Skipped scope entry (due to false predicate) at index 511, continuing at
525
Skipped scope entry (due to false predicate) at index 526, continuing at
540
Skipped scope entry (due to false predicate) at index 541, continuing at
555
Skipped scope entry (due to false predicate) at index 556, continuing at
570
Skipped scope entry (due to false predicate) at index 571, continuing at
585
Match failed at index 589
Continuing at 600
Match failed at index 601
Continuing at 615
Continuing at 616
Continuing at 617
Match failed at index 619
Continuing at 811
LLVM ERROR: Cannot select: 0x242d278: glue = EsenciaISD::SET_FLAG
0x242c618, 0x242c720, 0x242ce58 [ORD=3] [ID=11]
0x242c618: i32,ch = CopyFromReg 0x24009a0, 0x242c510 [ORD=1] [ID=9]
0x242c510: i32 = Register %vreg5 [ID=1]
0x242c720: i32 = Constant<3> [ID=2]
0x242ce58: i32 = Constant<20> [ID=8]
In function: fib
--
Rail Shafigulin
Software Engineer
Esencia Technologies
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