[llvm-dev] llc gives Segmentation fault at instruction selection in my own back end [was Re: Instruction selection gives "LLVM ERROR: Cannot select"]

RCU via llvm-dev llvm-dev at lists.llvm.org
Fri Feb 5 15:37:51 PST 2016


   Hello, Tim,
     I have attached the DOT file of the DAG before instruction selection starts.

     I found that the error with the NULL operand seems to be given by this code from 
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp .
2737   case OPC_RecordNode: {
2738     // Remember this node, it may end up being an operand in the pattern.
2739     SDNode *Parent = nullptr;
2740     if (NodeStack.size() > 1)
2741       Parent = NodeStack[NodeStack.size()-2].getNode();
2742     RecordedNodes.push_back(std::make_pair(N, Parent));
2743     continue;
2744   }

   Thank you,
     Alex

On 2/4/2016 7:57 PM, Tim Northover wrote:
> Hi Alex,
>
> On 4 February 2016 at 03:19, RCU <alex.e.susu at gmail.com> wrote:
>> But now I bumped into another serious problem: llc gives segmentation
>> fault while doing instruction select on the store.
>
> Are you building with assertions enabled? You can get segfaults still,
> but they're much rarer.
>
> Other than that, I'm afraid I don't know what the problem is. If
> you've got custom C++ to handle stores in some way, that would be the
> first place to look. It seems to be happening while creating a node,
> so it's obviously also worth investigating where Ops comes from there.
>
>> I can provide the entire DOT output with -view-isel-dags
>
> I'd certainly be willing to look at that file for anything malformed or odd.
>
> Cheers.
>
> Tim.
>
-------------- next part --------------
digraph "isel input for foo:entry" {
	rankdir="BT";
	label="isel input for foo:entry";

	Node0x1c81600 [shape=record,shape=Mrecord,label="{EntryToken|t0|{<d0>ch}}"];
	Node0x1cbd7d0 [shape=record,shape=Mrecord,label="{Register %vreg0|t1|{<d0>i64}}"];
	Node0x1cbda30 [shape=record,shape=Mrecord,label="{Register %vreg1|t3|{<d0>i64}}"];
	Node0x1cbdc90 [shape=record,shape=Mrecord,label="{Register %vreg2|t5|{<d0>i64}}"];
	Node0x1cbe280 [shape=record,shape=Mrecord,label="{undef|t10|{<d0>i64}}"];
	Node0x1cbfba0 [shape=record,shape=Mrecord,label="{Register %R0|t17|{<d0>i64}}"];
	Node0x1cbd900 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1}|CopyFromReg|t2|{<d0>i64|<d1>ch}}"];
	Node0x1cbd900:s0 -> Node0x1c81600:d0[color=blue,style=dashed];
	Node0x1cbd900:s1 -> Node0x1cbd7d0:d0;
	Node0x1cbdb60 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1}|CopyFromReg|t4|{<d0>i64|<d1>ch}}"];
	Node0x1cbdb60:s0 -> Node0x1c81600:d0[color=blue,style=dashed];
	Node0x1cbdb60:s1 -> Node0x1cbda30:d0;
	Node0x1cbddc0 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1}|CopyFromReg|t6|{<d0>i64|<d1>ch}}"];
	Node0x1cbddc0:s0 -> Node0x1c81600:d0[color=blue,style=dashed];
	Node0x1cbddc0:s1 -> Node0x1cbdc90:d0;
	Node0x1cbe3b0 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1|<s2>2}|load\<LD64[%1](align=4)\>|t11|{<d0>v8i64|<d1>ch}}"];
	Node0x1cbe3b0:s0 -> Node0x1c81600:d0[color=blue,style=dashed];
	Node0x1cbe3b0:s1 -> Node0x1cbd900:d0;
	Node0x1cbe3b0:s2 -> Node0x1cbe280:d0;
	Node0x1cbe4e0 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1|<s2>2}|load\<LD64[%3](align=4)\>|t12|{<d0>v8i64|<d1>ch}}"];
	Node0x1cbe4e0:s0 -> Node0x1c81600:d0[color=blue,style=dashed];
	Node0x1cbe4e0:s1 -> Node0x1cbdb60:d0;
	Node0x1cbe4e0:s2 -> Node0x1cbe280:d0;
	Node0x1cbf810 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1}|TokenFactor|t14|{<d0>ch}}"];
	Node0x1cbf810:s0 -> Node0x1cbe3b0:d1[color=blue,style=dashed];
	Node0x1cbf810:s1 -> Node0x1cbe4e0:d1[color=blue,style=dashed];
	Node0x1cbe610 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1}|add|t13|{<d0>v8i64}}"];
	Node0x1cbe610:s0 -> Node0x1cbe4e0:d0;
	Node0x1cbe610:s1 -> Node0x1cbe3b0:d0;
	Node0x1cbf940 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1|<s2>2|<s3>3}|store\<ST64[%6](align=4)\>|t15|{<d0>ch}}"];
	Node0x1cbf940:s0 -> Node0x1cbf810:d0[color=blue,style=dashed];
	Node0x1cbf940:s1 -> Node0x1cbe610:d0;
	Node0x1cbf940:s2 -> Node0x1cbddc0:d0;
	Node0x1cbf940:s3 -> Node0x1cbe280:d0;
	Node0x1cbfa70 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1|<s2>2}|load\<LD8[%C](align=4)\>|t16|{<d0>i64|<d1>ch}}"];
	Node0x1cbfa70:s0 -> Node0x1cbf940:d0[color=blue,style=dashed];
	Node0x1cbfa70:s1 -> Node0x1cbddc0:d0;
	Node0x1cbfa70:s2 -> Node0x1cbe280:d0;
	Node0x1cbfcd0 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1|<s2>2}|CopyToReg|t18|{<d0>ch|<d1>glue}}"];
	Node0x1cbfcd0:s0 -> Node0x1cbf940:d0[color=blue,style=dashed];
	Node0x1cbfcd0:s1 -> Node0x1cbfba0:d0;
	Node0x1cbfcd0:s2 -> Node0x1cbfa70:d0;
	Node0x1cbfe00 [shape=record,shape=Mrecord,label="{{<s0>0|<s1>1|<s2>2}|ConnexISD::RET_FLAG|t19|{<d0>ch}}"];
	Node0x1cbfe00:s0 -> Node0x1cbfcd0:d0[color=blue,style=dashed];
	Node0x1cbfe00:s1 -> Node0x1cbfba0:d0;
	Node0x1cbfe00:s2 -> Node0x1cbfcd0:d1[color=red,style=bold];
	Node0x0[ plaintext=circle, label ="GraphRoot"];
	Node0x0 -> Node0x1cbfe00:d0[color=blue,style=dashed];
}


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