[llvm-dev] [RFC] RISC-V backend
Renato Golin via llvm-dev
llvm-dev at lists.llvm.org
Wed Aug 17 16:08:44 PDT 2016
On 17 August 2016 at 10:14, Alex Bradbury via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> I am proposing the integration of a backend targeting the RISC-V ISA.
> In line with the proposed policy for adding a new target
> (https://reviews.llvm.org/D23162), RISC-V has a clear specification, multiple
> software models, and multiple FPGA implementations as well as prototype ASICs
> from various groups. At lowRISC (http://www.lowrisc.org/), inspired by our
> previous experience with the Raspberry Pi project, we are working towards
> creating a completely open source RISC-V SoC and producing low-cost
> development boards around it. Feel free to contact me off-list to discuss
> lowRISC further. LLVM is a key part of our development plan, and with
> community approval I would like to act as maintainer for the backend. The vast
> majority of my LLVM work over the past 6 years has sadly been out-of-tree, but
> I'm far from new to the project.
The policy has been updated and accepted by Chris and is now at:
Basically, in addition to the previous proposal, it requires a code
owner to come forward, which you just did. :)
Code owner: check
Compatible code: check
Policies: AFAICS, check
Docs / Impl: check
The code seem to have been reviewed and largely accepted, and your
responses to code review were quick and good.
>From what I can see, the RISC-V target & community checks all the boxes.
> It also provides a good basis for more detailed documentation on
> writing an LLVM backend (and making modifications to an existing one, e.g.
> making it much easier for a research group wanting to explore RISC-V changes).
This would be fantastic!
> I've obviously spent a lot of time with the MC layer recently, and I'd be
> happy to put that to use in helping review MC patches for other archs.
This also checks the box for "helpful community". :)
> Mini development roadmap:
> * Complete MC layer (supporting up to RV32+RV64G at least)
> * There is currently no specification for supported RISC-V assembly syntax,
> mnemonics etc. The ideal solution may not always be "whatever the GCC port
> currently does", so some aspect of this will involve discussions with the
> wider RISC-V software community.
Maybe some more documentation is in order, but this can start slow and
converge to a future standard.
One problem that might happen is that GNU asm output will have to be
accepted, so in doubt, following what they do would be the least
amount of work. But in the long run, you'll want something consistent
and well written (to be considered the go-to back-end), and if the
RISC-V community decides LLVM is the default compiler, following an
agreed spec, then GCC will have no option but to follow the spec.
> * Codegen
> * Compressed instruction set support (RVC)
> * Benchmarking and comparison to GCC RISC-V (and potentially other archs)
What about buildbots?
I'm assuming "check-all" would be enough for now, but you'll have to
have at least one buildbot that builds the back-end (which for now
will be experimental, and will need an additional CMake flag).
But in the long run, you'll want to run the test-suite, even if on a
simulator, and who knows, maybe even self-host Clang in your target!
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