[llvm-dev] RFC: speedups with instruction side-data (ADCE, perhaps others?)

[Pete Cooper via llvm-dev]

> On Sep 14, 2015, at 2:49 PM, Matt Arsenault via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> On 09/14/2015 02:47 PM, escha via llvm-dev wrote:
>> I would assume that it’s just considered to be garbage. I feel like any sort of per-pass side data like this should come with absolute minimal contracts, to avoid introducing any more inter-pass complexity.
>  I would think this would need to be a verifier error if it were ever non-0
+1

Otherwise every pass which ever needs this bit would have to first zero it out just to be safe, adding an extra walk over the whole functions.

Of course otherwise the pass modifying it will have to zero it, which could also be a walk over the whole function.  So either way you have lots iterate over, which is why i’m weary of this approach tbh.
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