[llvm-dev] [AMDGPU] AMDGPUAsmParser fails to parse several instructions

Matt Arsenault via llvm-dev llvm-dev at lists.llvm.org
Sat Oct 24 08:17:35 PDT 2015

> On Oct 24, 2015, at 10:50 AM, 李弘宇 <zhenlinospirit at gmail.com> wrote:
> I have no idea what to do the work-around. To me the modifier is set when the register has absolute or negate.

Yes, this is what the modifiers are.

> I traced the code and thought that the problem occurs in the for loop to empty the modifiers for each source (in the AMDGPUAsmParser::parseOperand around line 1040). If I add an if statement like
> if(RegOp.isInlineImm()) // because 0.5 is this case
>     contiune;
> before the statement to empty the modifier (RegOp.setModifiers(0);), 
> it obvious does not work and cause the other matching fails. Does it mean to modify other files in other places, such as the VOP3Inst in the SIInstrInfo.td, or is this nothing to do with the MatchOperandParserImpl method or the other tablegen'd files.
> I'll be grateful for any idea you might give me to work around this.
> Regards,

The workaround is to either move the 0.5 into a register and use or to apply the negate to the other operand first, e.g.:

v_mov_b32 v0, 0.5
v_mad_f32 v9, v0, v5, -v8

which will have a smaller encoding than the alternative of doing the fneg first.

The crash is easy enough to fix by checking isReg() before the setModifiers, but then the instruction is incorrectly rejected. I’m not really sure what’s going on with that right now, but I’m guessing it has to do with the way the modifiers are part of the same parsed operand, but separate in the MCInst’s operands and the missing modifier operand isn’t being added for immediates. I’m not really sure the right way to fix this.

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