[llvm-dev] [AMDGPU] AMDGPUAsmParser fails to parse several instructions
李弘宇 via llvm-dev
llvm-dev at lists.llvm.org
Sat Oct 24 07:50:56 PDT 2015
Thanks you. I'm new to LLVM backend, so the help is much appreciated.
On Sat, Oct 24, 2015 at 2:12 AM, Matt Arsenault <arsenm2 at gmail.com> wrote:
> > On Oct 23, 2015, at 3:36 AM, 李弘宇 via llvm-dev <llvm-dev at lists.llvm.org>
> > The first line has the following error message:
> > sop1-playground.s:1:15: error: invalid immediate: only 32-bit values are
> > s_mov_b32 s0, 0xfe5163ab
> I’ve fixed this problem in r251132.
Thanks for the reply and the quick fix of negative 32-bit immediate.
> > The second line of the assembly has the assertion fail:
> > llvm-mc:
> void (anonymous namespace)::AMDGPUOperand::setModifiers(unsigned int):
> Assertion `isReg()' failed.
> > and reports that 0.5 is "error: invalid operand for instruction"
> > v_mad_f32 v9, 0.5, v5, -v8
> There is a bug with operand parsing when you have immediate operands and
> source modifiers. I haven’t fixed this yet, but you can work around it for
> now by not using the source modifier.
I have no idea what to do the work-around. To me the modifier is set when
the register has absolute or negate. I traced the code and thought that the
problem occurs in the for loop to empty the modifiers for each source (in
the AMDGPUAsmParser::parseOperand around line 1040). If I add an if
if(RegOp.isInlineImm()) // because 0.5 is this case
before the statement to empty the modifier (RegOp.setModifiers(0);),
it obvious does not work and cause the other matching fails. Does it mean
to modify other files in other places, such as the VOP3Inst in the
SIInstrInfo.td, or is this nothing to do with the MatchOperandParserImpl
method or the other tablegen'd files.
I'll be grateful for any idea you might give me to work around this.
李弘宇 (Li, Hong-Yu)
Department of Computer Science & Information Engineering
National Taiwan University
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