[llvm-dev] Hexagon, DFAPacketizer and instruction expansion

[Rail Shafigulin via llvm-dev]

I'm using a Hexagon's packetizer as an example to packetize instructions
for my custom VLIW. The problem that I'm facing is that my target as it
turns out doesn't have all the instructions expanded by the time
packetization happens (for example I have a RET instruction which gets
expanded into a write to a register and a jump/branch). I'm wondering if
Hexagon is experiencing the same issue and how it is solved? And if it
doesn't experience the same what would be the recommendation on solving
this problem? At the moment, my packetization pass is the last one in
MyTargetPassConfig::addPreEmitPass()

Any help is appreciated.

-- 
R
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