[llvm-dev] Help making 'narrow instruct microcode' Backend

[escha via llvm-dev]

> On Nov 12, 2015, at 8:43 AM, James R. Byerly via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> I've been experimenting with llvm/clang as a user for a while now, but now
> I'm interested in writing my own backend. I'm also developing the target
> architecture (maybe to go in an fpga eventually) and I'm intentionally
> making it extremely simple. I think of it as a narrow microcode, because
> (for example) performing an add requires a sequence of instructions like:
> set aluin1 = r1
> set aluin2 = r2
> aluop add
> set r3 = aluout

This sounds very similar to some sorts of existing VLIW architectures, which may look something like this:

// START BUNDLE
{
// input phase
s0 = <some input>
s1 = <some input>
[…]
sN = <some input>
// phase 0
t0 = <some operation using s registers>
t1 = <some operation using s registers>
[…]
tN = <some operation using s registers>
// phase 1
// stuff using t registers
[…]
// phase N
// stuff using t registers
// output phase
rX = t0
rY = t1
rZ = t2
}
// END BUNDLE

Of course, the bundles can be as complex or simple as you like; they could have just one phase and one operation, for example. Either way, this sort of thing where it defines inputs, then defines an instruction, then defines outputs, sounds very much like a problem for VLIW bundles. VLIW tends to be very simple/“close to the metal” insomuch as the bits in the instruction encoding directly map to muxes between the phases, i.e. selecting which register is passed from where to where.

—escha