[llvm-dev] Help making 'narrow instruct microcode' Backend

[James R. Byerly via llvm-dev]

I've been experimenting with llvm/clang as a user for a while now, but now
I'm interested in writing my own backend. I'm also developing the target
architecture (maybe to go in an fpga eventually) and I'm intentionally
making it extremely simple. I think of it as a narrow microcode, because
(for example) performing an add requires a sequence of instructions like:
set aluin1 = r1
set aluin2 = r2
aluop add
set r3 = aluout

I've started implementing the backend in clang, and I got this basic
example working by modifying my backend's implementation of
SelectionDAGISel::Select to handle ISD::ADD and transform it into the
above 4-instruction sequence. However, I'd like to expand the architecture
to have more than 1 alu, with one set of alu registers for each alu (ex
aluAin1, aluAin2, aluAout, and aluBin1, aluBin2, aluBout). I'd also like
to have llvm's register allocation and instruction scheduling select which
alu to use at what time, but I don't think I can acomplish this with my
current approach.

One thought I had was making the aluin1/2 and aluout subregisters of a
larger register, and then making multiple instances of that register type
and a class for the larger registers, but I'm not sure how to tell llvm
that it should use the multi-instruction sequence for ADD. Is there a way
to do it in the Select function like I did for 1, but with virtual
registers so the allocator/scheduler can pick which alu to use?

Any information on how I might implement the super/subregister solution or
any alternative approaches to implementing a backend for this architecture
are greatly appreciated.