[LLVMdev] fake an extend for "SEXT" signal

[Matt Arsenault]

> On Jul 9, 2015, at 12:54 PM, kewuzhang <kewu.zhang at amd.com> wrote:
> 
> HI Guys, 
> 
> I have a “normal” load instruction like the following:
> "
> %2 = load i16 addressspace(1) * %1, align 2, !tbaa !10
> “
> where the metadata tbaa is telling me that the source is a signed short.
> So I want to do a “signed load”  when I am lowering the Load operation.( LLVM now just tells me “load i16” without any sign or unsign info)

This isn’t want the TBAA metadata is for. You shouldn’t be trying to decide if a type is signed or not, especially not using metadata which is likely to not be present. If a load is used in a sign extended way, the DAG node will report that it’s extension type is SEXTLOAD by the time it reaches the custom lowering. You should not be concerned with the C type this happens to correspond to, only the specific load operation the target is asked to handle.


> 
> questions:
> (1)  How could I pass the “sign” flag to customLowering?
You should only be checking if a load is a sextload.


> 
> (2) I wanted to “trick” llvm by “ inserting an extend, and followed by an truncate” instructions, so I am hoping that LLVM can send me a “SextLoad” and “Truncate”.
> But LLVM is smart enough, it just ignores my effort. 
> 
> Is there anyway to “workaround” this problem?
> 
> best
> kevin

If you really want to hack around folding conversions, you would need to insert a new node type / target node that the DAG combiner doesn’t understand

-Matt


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