[LLVMdev] fake an extend for "SEXT" signal

[Krzysztof Parzyszek]

On 7/9/2015 2:54 PM, kewuzhang wrote:
>
> I have a “normal” load instruction like the following:
> "
>   %2 = load i16 addressspace(1) * %1, align 2, !tbaa !10
> “
> where the metadata tbaa is telling me that the source is a signed short.
> So I want to do a “signed load”  when I am lowering the Load operation.( LLVM now just tells me “load i16” without any sign or unsign info)

The only way you can get a "signed load" is if you have an extending 
load which performs a sign-extension.  This would usually be a result of 
having a load followed by a sext.  What's important here is that sext 
produces a value of a different type than the input.  If you insert a 
sext from i16 after the load, you will end up with a value of a wider 
type, say i32.  Similarly, trunc will change the type to something 
shorter, in your case it could be from i32 back to i16.  This 
combination is a no-op and LLVM will remove it.

If you insert only the extension then you will have to change the rest 
of the program to accomodate the new value type.


> questions:
> (1)  How could I pass the “sign” flag to customLowering?

You could make the i16 type be not-legal.  Then any load of i16 will be 
replaced with an extload to a wider legal type.  Then you can have a 
selection pattern that picks sign-extending load for extload.


-Krzysztof


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