[LLVMdev] Backend Tablegen Instruction Definition

[Tim Northover]

Hi John,

On 10 January 2015 at 17:33, John Leidel (jleidel) <jleidel at micron.com> wrote:
> def RDCYCLE: InstRISCV<4, (outs GR32:$dst), (ins), ([set GC32:$dst])>{

I think the problem is that pattern. For your purposes just using an
empty pattern, "[]", ought to be fine to begin with.

If and when you do decide it needs to be selected, you'll probably go
via an intrinsic at the IR level. Something like "(set GR32:$dst,
int_riscv_read_cycle)", though I've not actually ever tried to match
an intrinsic with *no* arguments before, so you may need to modify
that slightly.

Cheers.

Tim.