[LLVMdev] Backend Tablegen Instruction Definition

[John Leidel (jleidel)]

All, in working through the RISCV LLVM backend, I’m running into some trouble in defining the instruction formats for the system instruction.  The system instructions follow a pre-defined instruction template (type-I), but differ in that they have no input registers (only the target).  The system instructions are defined as: 

rdcycle Rt

I’ve defined a stand-alone instruction definition (as opposed to using the type-I template) that is as follows: 
//rdcycle
def RDCYCLE: InstRISCV<4, (outs GR32:$dst), (ins), ([set GC32:$dst])>{

        field bits<32> Inst;

        bits<5> dst;

        let Inst{31-20} = 0b000000000000;
        let Inst{19-15} = 0b00000;
        let Inst{14-12} = 0b010;
        let Inst{11- 7} = dst;
        let Inst{6 - 0} = 0b1110011;
      }

However, the compilation fails with the follow: 
llvm[3]: Building RISCV.td instruction information with tblgen
llvm-tblgen: /home/jleidel/dev/working/jleidel-riscv-llvm/riscv-trunk/utils/TableGen/CodeGenDAGPatterns.cpp:161
ode::ApplyTypeConstraints(llvm::TreePattern &, bool): Assertion `getNumChildren() >= 2 && "Missing RHS of a set

Does the codegen permit me to write instruction definitions manually in this manner, or do I need to virtualize the instruction given the lack of RHS args?  

cheers
john 

John D. Leidel