[llvm-dev] get instruction destination register

fateme Hoseini via llvm-dev llvm-dev at lists.llvm.org
Mon Dec 21 18:40:30 PST 2015

Thank you so much.
I want to use ARM::R0, because I'm going to need this style for evaluating
opcodes as well. Forgive me if this is a stupid question question, but I
don't know how to include this information in my code. I think I have to
include "ARMBaseInfo.h", and
#include "../lib/Target/ARM/ARMBaseInfo.h" does not work!

On Mon, Dec 21, 2015 at 7:29 PM, Tim Northover <t.p.northover at gmail.com>

> On 21 December 2015 at 13:24, fateme Hoseini <hoseini.f at gmail.com> wrote:
> > Thank you for your thorough reply. So, based on your reply I get every
> > operand and check them to be (isDef && !isimplicit). Now my problem is
> that
> > it gives me the physical register number.i.e, for example, instead of
> r0, it
> > return %physreg66. Could you please help me on how to convert these
> physical
> > register number to the ARM related register? I mean the 15 GPRs in ARM.
> You should be able to compare them to the generated enum:
> "Op->getReg() == ARM::R0" for example. Alternatively you could use
> "MCRegisterInfo::getEncodingValue" on "Op->getReg()", which would
> return 0-15 for the basic registers.
> Cheers.
> Tim.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151221/39065037/attachment.html>

More information about the llvm-dev mailing list