[llvm-dev] get instruction destination register

Tim Northover via llvm-dev llvm-dev at lists.llvm.org
Mon Dec 21 16:29:09 PST 2015

On 21 December 2015 at 13:24, fateme Hoseini <hoseini.f at gmail.com> wrote:
> Thank you for your thorough reply. So, based on your reply I get every
> operand and check them to be (isDef && !isimplicit). Now my problem is that
> it gives me the physical register number.i.e, for example, instead of r0, it
> return %physreg66. Could you please help me on how to convert these physical
> register number to the ARM related register? I mean the 15 GPRs in ARM.

You should be able to compare them to the generated enum:
"Op->getReg() == ARM::R0" for example. Alternatively you could use
"MCRegisterInfo::getEncodingValue" on "Op->getReg()", which would
return 0-15 for the basic registers.



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