[llvm-dev] RFC for a design change in LoopStrengthReduce / ScalarEvolution

Sanjoy Das via llvm-dev llvm-dev at lists.llvm.org
Mon Aug 17 22:39:23 PDT 2015

> My interpretation of this problem was that LSR starts analysis with an
> SCEV that counts down toward zero even in an upward counting loop.  A
> more natural fit would be an initial IV going from 0 to some limit,
> but there does not seem to be a way to express this sort of SCEV.  The
> initial condition puts an artificially high cost on solutions with
> upward counting registers since none match the "free" down counting
> SCEV.  Notice the weird 'dec %eax' showing up as an artifact.  The
> best solution with base-index scale 4 addressing was considered by
> LSR, but incorrectly deemed to be too expensive.
> Is this the same LSR problem you describe?

No, these two issues look unrelated.

-- Sanjoy

More information about the llvm-dev mailing list