[llvm-dev] Working with X86 registers in MachineInstr
Ethan J. Johnson via llvm-dev
llvm-dev at lists.llvm.org
Wed Aug 12 09:51:02 PDT 2015
From: Quentin Colombet [mailto:qcolombet at apple.com]
Sent: Wednesday, August 12, 2015 12:42 PM
To: Ethan J. Johnson <ejohns48 at cs.rochester.edu <mailto:ejohns48 at cs.rochester.edu> >
Cc: llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> ; John Criswell <jtcriswel at gmail.com <mailto:jtcriswel at gmail.com> >
Subject: Re: [llvm-dev] Working with X86 registers in MachineInstr
On Aug 12, 2015, at 8:35 AM, John Criswell via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > wrote:
I believe that the enum values X86::<reg> correspond to the integers that you're seeing. For example, X86::RAX is %rax, X86::RBX is %rbx, etc.
Those numbers are virtual or physical registers. You can tell by using TargetRegisterInfo::isPhyscalRegister.
Walk through the operands, and check:
- If the operand is a register.
- If it is a use or def.
Some operands are also register masks, those give you the set of registers that are preserved through that instruction, i.e., the complement gives you a bunch of new “definitions”.
Anyway, look into the AArch64CollectLOH pass, you’ll see all of that in action. The register allocator code on the other hand is of little use for you, as the liveness information is only for virtual registers and the infrastructure does not work with allocated code.
Thanks! This sounds like exactly what I’m looking for. I’ll give it a look.
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the llvm-dev