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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span style='font-size:11.0pt;font-family:"Calibri",sans-serif'> Quentin Colombet [<a href="mailto:qcolombet@apple.com">mailto:qcolombet@apple.com</a>] <br><b>Sent:</b> Wednesday, August 12, 2015 12:42 PM<br><b>To:</b> Ethan J. Johnson <<a href="mailto:ejohns48@cs.rochester.edu">ejohns48@cs.rochester.edu</a>><br><b>Cc:</b> <a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>; John Criswell <<a href="mailto:jtcriswel@gmail.com">jtcriswel@gmail.com</a>><br><b>Subject:</b> Re: [llvm-dev] Working with X86 registers in MachineInstr<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><div><blockquote style='margin-top:5.0pt;margin-bottom:5.0pt'><div><p class=MsoNormal>On Aug 12, 2015, at 8:35 AM, John Criswell via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>> wrote:<o:p></o:p></p></div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif;background:white'>I believe that the enum values X86::<reg> correspond to the integers that you're seeing. For example, X86::RAX is %rax, X86::RBX is %rbx, etc.</span><o:p></o:p></p></div></blockquote><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Those numbers are virtual or physical registers. You can tell by using TargetRegisterInfo::isPhyscalRegister.<o:p></o:p></p></div><p class=MsoNormal style='margin-left:5.25pt'><span style='font-size:9.0pt;font-family:"Helvetica",sans-serif'><o:p> </o:p></span></p><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal>Walk through the operands, and check:<o:p></o:p></p></div><div><p class=MsoNormal>- If the operand is a register.<o:p></o:p></p></div><div><p class=MsoNormal>- If it is a use or def.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Some operands are also register masks, those give you the set of registers that are preserved through that instruction, i.e., the complement gives you a bunch of new “definitions”.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal style='margin-left:5.25pt'>Anyway, look into the AArch64CollectLOH pass, you’ll see all of that in action. The register allocator code on the other hand is of little use for you, as the liveness information is only for virtual registers and the infrastructure does not work with allocated code.<span style='color:#1F497D'><o:p></o:p></span></p></div><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Thanks! This sounds like exactly what I’m looking for. I’ll give it a look.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Ethan Johnson<o:p></o:p></span></p></div></body></html>