[LLVMdev] Adding masked vector load and store intrinsics

Demikhovsky, Elena elena.demikhovsky at intel.com
Sun Oct 26 00:07:06 PDT 2014


We may receive less optimal code on other targets as a result. User may want optimize a sequence of scalar instructions after vectorization did not pass.

-           Elena

From: shahid shahid [mailto:shahid77c at yahoo.com]
Sent: Saturday, October 25, 2014 17:53
To: Demikhovsky, Elena; llvmdev at cs.uiuc.edu
Cc: dag at cray.com
Subject: Re: [LLVMdev] Adding masked vector load and store intrinsics

Hi Elena,

Nice to see that your thinking are quite similar with mine.

Do you plan to generate this intrinsic in Loop Vectorizer based on subtarget feature?

If so, it would be better to let it generate here in target independent manner.Later on,
during lowering, based on the availability of target support for masked ops you can decide
either to scalarize or generate the target masked ops instruction.

Shahid
On Friday, October 24, 2014 4:59 PM, "Demikhovsky, Elena" <elena.demikhovsky at intel.com<mailto:elena.demikhovsky at intel.com>> wrote:

Hi,

We would like to add support for masked vector loads and stores by introducing new target-independent intrinsics. The loop vectorizer will then be enhanced to optimize loops containing conditional memory accesses by generating these intrinsics for existing targets such as AVX2 and AVX-512. The vectorizer will first ask the target about availability of masked vector loads and stores. The SLP vectorizer can potentially be enhanced to use these intrinsics as well.

The intrinsics would be legal for all targets; targets that do not support masked vector loads or stores will scalarize them.
The addressed memory will not be touched for masked-off lanes. In particular, if all lanes are masked off no address will be accessed.

  call void @llvm.masked.store (i32* %addr, <16 x i32> %data, i32 4, <16 x i1> %mask)

  %data = call <8 x i32> @llvm.masked.load (i32* %addr, <8 x i32> %passthru, i32 4, <8 x i1> %mask)

where %passthru is used to fill the elements of %data that are masked-off (if any; can be zeroinitializer or undef).

Comments so far, before we dive into more details?

Thank you.

- Elena and Ayal


---------------------------------------------------------------------
Intel Israel (74) Limited
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

_______________________________________________
LLVM Developers mailing list
LLVMdev at cs.uiuc.edu<mailto:LLVMdev at cs.uiuc.edu>        http://llvm.cs.uiuc.edu<http://llvm.cs.uiuc.edu/>
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20141026/0a41fcc5/attachment.html>


More information about the llvm-dev mailing list